Soc Physical Design Engineer
A fabless ASIC / SoC and silicon IP provider
Responsibilities
- ASIC physical implementation by using automatic place and route tools
- Floor planning, powerplan synthesis, clock tree synthesis, timing closure, routing, and post-route optimization
- Physical verification signoff including DRC, LVS, ERC, Antenna and ESD
- Coordinate cross-site communication and coordination among internal supporting groups
Requirements
- Familiar with Cadence Innovus or Synopsys ICC flow
- Familiar with timing closure, IR drop analysis and physical verification
- Excellent team and interpersonal skills
- BS or MS degree in EE or CS related
- Good English communication skills
- Min 3 years working experience
- Candidate with lesser experience will be considered for junior position
- Interview process: 2 rounds ( HR & Technical)
Benefits
- Bonus: 13th month + Average 3 to 6 months performance bonus/ year
Annual Leave 16 days + additional project compensation leave - BaoViet Medical Insurance for spouse and all children (from Day 1 of probation)
- Annual Company Trip, Laptop
- Monthly Birthday Celebration, Quarterly Lunch/Dinner
- Working time: 9~6pm, Mon to Fri in Dist 1, HCMC
- Business Travel to Taiwan HQ
Job Features
Job Category | IT jobs |
Phone | 0866 047046 |
[email protected] |