Memory Circuit Design Engineer

A fabless ASIC / SoC and silicon IP provider
Full time
Ho Chi Minh
Posted 2 years ago


  • Design, Optimization and Verification of IP Memory Compiler
  • Design include High-speed, High-density or Low-Power variant
  • Actively participate in design methodology and QA system improvement
  • Cooperate with Layout and CAD engineers for optimal schedule
  • Assist testchip team in silicon verification and provide silicon validation report
  • Provide mentorship and guidance to junior engineers


  • Solid knowledge on SRAM architecture and design methodology
  • Solid knowledge on device physics, process variation and SRAM bit cell behavior
  • Familiar with Performance, Power and Area (PPA) design optimization
  • Familiar with Timing/Power characterization, Function Verification and other SRAM compiler QA tools setup
  • BS or MS degree in EE or CS related
  • Good English communication skills
  • Experience in FinFET is a plus
  • Min 3 years working experience
  • Candidate with lesser experience will be considered for junior position


  • Bonus: 13th month + Average 3 to 6 months performance bonus/ year
    Annual Leave 16 days + additional project compensation leave
  • Bao Viet Medical Insurance for spouse and all children (from Day 1 of probation)
  • Annual Company Trip, Laptop
  • Monthly Birthday Celebration, Quarterly Lunch/Dinner
  • Working time: 9~6pm, Mon to Fri in Dist 1, HCMC
  • Business Travel to Taiwan HQ

Job Features

Job CategoryIT jobs
Phone0866 047046
Email[email protected]

Apply Online