Memory Layout Design Engineer

A fabless ASIC / SoC and silicon IP provider
Full time
Ho Chi Minh
Posted 2 years ago


  • Cell & block level layout, macro planning and interconnect
  • Physical verification (LVS, DRC, ERC, EMIR)
  • Actively participate in layout QA methodology and QA system improvement
  • Cooperate with designers for optimal Performance, Power and Area (PPA)
  • Provide mentorship and guidance to junior engineers


  • Familiar with memory layout such as SRAM, ROM or TCAM
  • Familiar with Floor-planning, P/G mesh planning, signal routing and matching layout
  • Familiar with Cadence/Synopsys layout editor and physical verification tools
  • Experience in schedule estimation
  • BS degree in EE or CS related
  • Good English communication skills
  • Experience in FinFET is a plus
  • Min 3 years working experience
  • Candidate with lesser experience will be considered for junior position
  • Interview process: 2 rounds ( HR & Technical)


  • Bonus: 13thmonth + Average 3 to 6 months performance bonus/ year
    Annual Leave 16 days + additional project compensation leave
  • Bao Viet Medical Insurance for spouse and all children (from Day 1 of probation)
  • Annual Company Trip, Laptop
  • Monthly Birthday Celebration, Quarterly Lunch/Dinner
  • Working time: 9~6pm, Mon to Fri in Dist 1, HCMC
  • Business Travel to Taiwan HQ

Job Features

Job CategoryIT jobs

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