Roles & Responsibilities

• You will develop, segmentation, and campaign analytical features using Python, Go, Clickhouse, Redis, Postgrest, Kafka, and much more.
  • For example, our clients use segmentation to personalize user’s experiences. You may introduce new adjust existing business logic of our segmentation, improve the performance of million users segmentation by updating daily processes, or you may help us to research and implement a new execution/scheduling engine to fairly distribute resources among our happy clients.
• You will take your hand dirty on PMB – Metrics Builder, a core component of our data engineering platform.
  • PMB may process the calculation and updating of thousand metrics over TBs data volume in both real-time and batch orientations with interactive drag/drop UI.
• You will review the code of your peers and they’ll review yours. We are going to get high code quality standards and the four-eyes principle is a must!
• You will start on easier, self-contained projects and once you feel at home, you can move to real beasts. Challenging, complex projects that will leave a mark – we have plenty of those.
• Last but not least, we have some kind of legacy code that are being replaced by better things, but somehow we still have to maintain them in the dark.

Job requirements:

• You have experience with Python and a solid grasp of engineering practices.
  • We use FastAPI, Faust, Dask, Numpy, and Pandas for Python. You don’t need to know all of these tools but you should be a fast-picking up person to learn.
• If you have an experience with Go or C++, that’s a big advantage.
• You are able to learn and adapt. It’ll be handy while exploring new tech, navigating our not-so-small code base, or when iterating on our team processes.
• You are willing to learn about the monitoring of the production systems, database internals, and the development of distributed systems.
• Experienced in MPP or Big Data Platform tools ( Spark/Flink/Presto ) is a big plus.

An optional but good plus if candidates own below experience:

• Martech experience (DMPs, DSP, Emails, CDP, CDXP …).
• Work experience in B2B SaaS in online retail/e-commerce analytics, and marketing.
• Work experience in engineering team in retail/commerce companies.

Special Benefits:

• Work directly with industry experts and market leaders in DX, CX, digital-data-tech as well as named customers.
• Being a part of the awesome team building Company Data CDP – the pioneering science-first customer data & experience platform.
• Flexible, open, and innovative environment.

Responsibilities

• ASIC physical implementation by using automatic place and route tools
• Floor planning, powerplan synthesis, clock tree synthesis, timing closure, routing, and post-route optimization
• Physical verification signoff including DRC, LVS, ERC, Antenna and ESD
• Coordinate cross-site communication and coordination among internal supporting groups

Requirements

• Familiar with Cadence Innovus or Synopsys ICC flow
• Familiar with timing closure, IR drop analysis and physical verification
• Excellent team and interpersonal skills
• BS or MS degree in EE or CS related
• Good English communication skills
• Min 3 years working experience
• Candidate with lesser experience will be considered for junior position
• Interview process: 2 rounds ( HR & Technical)

Benefits

• Bonus: 13th month + Average 3 to 6 months performance bonus/ year
  Annual Leave 16 days + additional project compensation leave
• BaoViet Medical Insurance for spouse and all children (from Day 1 of probation)
• Annual Company Trip, Laptop
• Monthly Birthday Celebration, Quarterly Lunch/Dinner
• Working time: 9~6pm, Mon to Fri in Dist 1, HCMC
• Business Travel to Taiwan HQ

Responsibilities

• Main technical contact window and consultant of ASIC implementation from RTL-in/netlist-in to tapeout
• Perform project management and coordinate among internal supporting groups
• DFT implementation, including MBIST, DFT insertion, JTAG and ATPG generation
• STA signoff
• Advice customers on technical issues related to floorplan, sdc, clock tree, package, power

Requirements

• Familiar with PrimeTime, Debussy, Verilog-XL, Design Compiler and Formal Verification tools
• Excellent team and interpersonal skills
• BS or MS degree in EE or CS related
• Good English communication skills
• Experience in DFT is a plus
• Min 3 years working experience
• Candidate with lesser experience will be considered for junior position
• Interview process: 2 rounds ( HR & Technical)

Benefits

• Bonus: 13^thmonth + Average 3 to 6 months performance bonus/ year
  Annual Leave 16 days + additional project compensation leave
• Bao Viet Medical Insurance for spouse and all children (from Day 1 of probation)
• Annual Company Trip, Laptop
• Monthly Birthday Celebration, Quarterly Lunch/Dinner
• Working time: 9~6pm, Mon to Fri in Dist 1, HCMC
• Business Travel to Taiwan HQ

Responsibilities

• Cell & block level layout, macro planning and interconnect
• Physical verification (LVS, DRC, ERC, EMIR)
• Actively participate in layout QA methodology and QA system improvement
• Cooperate with designers for optimal Performance, Power and Area (PPA)
• Provide mentorship and guidance to junior engineers

Requirements

• Familiar with memory layout such as SRAM, ROM or TCAM
• Familiar with Floor-planning, P/G mesh planning, signal routing and matching layout
• Familiar with Cadence/Synopsys layout editor and physical verification tools
• Experience in schedule estimation
• BS degree in EE or CS related
• Good English communication skills
• Experience in FinFET is a plus
• Min 3 years working experience
• Candidate with lesser experience will be considered for junior position
• Interview process: 2 rounds ( HR & Technical)

Benefits

• Bonus: 13^thmonth + Average 3 to 6 months performance bonus/ year
  Annual Leave 16 days + additional project compensation leave
• Bao Viet Medical Insurance for spouse and all children (from Day 1 of probation)
• Annual Company Trip, Laptop
• Monthly Birthday Celebration, Quarterly Lunch/Dinner
• Working time: 9~6pm, Mon to Fri in Dist 1, HCMC
• Business Travel to Taiwan HQ

Responsibilities

• Design, Optimization and Verification of IP Memory Compiler
• Design include High-speed, High-density or Low-Power variant
• Actively participate in design methodology and QA system improvement
• Cooperate with Layout and CAD engineers for optimal schedule
• Assist testchip team in silicon verification and provide silicon validation report
• Provide mentorship and guidance to junior engineers

Requirements

• Solid knowledge on SRAM architecture and design methodology
• Solid knowledge on device physics, process variation and SRAM bit cell behavior
• Familiar with Performance, Power and Area (PPA) design optimization
• Familiar with Timing/Power characterization, Function Verification and other SRAM compiler QA tools setup
• BS or MS degree in EE or CS related
• Good English communication skills
• Experience in FinFET is a plus
• Min 3 years working experience
• Candidate with lesser experience will be considered for junior position

Benefits

• Bonus: 13^th month + Average 3 to 6 months performance bonus/ year
  Annual Leave 16 days + additional project compensation leave
• Bao Viet Medical Insurance for spouse and all children (from Day 1 of probation)
• Annual Company Trip, Laptop
• Monthly Birthday Celebration, Quarterly Lunch/Dinner
• Working time: 9~6pm, Mon to Fri in Dist 1, HCMC
• Business Travel to Taiwan HQ